1. Field of the Invention
This invention relates to an improved method and system for acquiring and maintaining phase synchronism between two digital signals (i.e., a data signal and a clock signal), and more particularly, to a system that can be economically implemented in very large scale integrated circuits.
2. Cross Reference to Related Applications
The present United States patent application is related to the following co-pending United States patent applications incorporated herein by reference:
Application Ser. No. 08/261,515, filed Jun. 17, 1994 (attorney Docket No. PO9-93-054), entitled "Self-Timed Interface," and assigned to the assignee of this application.
Application Ser. No. 08/261,522, filed Jun. 17, 1994 (attorney Docket No. PO9-93-056), entitled "Multiple Processor Link," and assigned to the assignee of this application.
Application Ser. No. 08/261,561, filed Jun. 17, 1994 (attorney Docket No. PO9-93-057), entitled "Enhanced Input-Output Element," and assigned to the assignee of this application.
Application Ser. No. 08/262,603, filed Jun. 17, 1994 (attorney Docket No. PO9-93-058), entitled "Massively Parallel System," and assigned to the assignee of this application.
Application Ser. No. 08/261,523, filed Jun. 17, 1994 (attorney Docket No. PO9-93-059), entitled "Attached Storage Media Link," and assigned to the assignee of this application.
Application Ser. No. 08/261,641, filed Jun. 17, 1994 (attorney Docket No. PO9-93-060), entitled "Shared Channel Subsystem," and assigned to the assignee of this application.
3. Description of the Prior Art
Digital phase locked loops are known and used in the prior art to acquire and maintain phase synchronization between a digital data signal and a digital clock signal. Typically, in a digital phase locked loop, input data is delayed by incremental fixed time intervals to generate multiple phases of the data signal. These phases are individually sampled and compared with the digital clock signal. In making this comparison, a circuit detects a phase difference between the clock signal and each of the multiple phases of the data signal. The comparison circuit generates a control signal that selects one of the multiple phases best suited to be sampled by the clock signal. In such prior art digital phase locked loops, each delay element is sampled and individually compared with the clock signal. In general, performance of the loop is proportional to the number of delay elements or taps and a large amount of circuitry is required to make the comparisons and generate a control signal. Then, too, in prior art systems, filtering significantly increases the number of circuits since each element must be individually sampled, interrogated, and stored.